1. Field of the Invention
The present invention relates to an information processing device and an information processing method. More particularly, the present invention relates to an information processing device and an information processing method for performing a system boot by executing a program stored in a storage device, such as a NAND-type flash memory or the like, which has a possibility that a invalid block is originally included and a possibility that a invalid block occurs later.
2. Description of the Background Art
Flash memories can be roughly divided into NOR type and NAND type. The NOR-type flash memory has an advantage that it can be randomly accessed on a byte-by-byte basis, but has a disadvantage that it is expensive and its packaging density is low, as compared to the NAND-type flash memory.
On the other hand, the NAND-type flash memory is a memory in which invalid blocks are acceptable if the proportion of the invalid blocks is smaller than or equal to a predetermined value. Therefore, when data is written into or read from the NAND-type flash memory, the positions of invalid blocks need to be managed. In addition, the NAND-type flash memory can be accessed only sequentially, and an error detection/correction process is required after a read operation. Despite such a drawback, the NAND-type flash memory is advantageously inexpensive and advantageously has a high level of packaging density as compared to the NOR type flash memory.
There is a known information processing device which employs a NAND-type flash memory having such an advantage, as a storage device for storing an initial program which is executed during a system boot. In such a conventional information processing device, in order to execute a program stored in a low reliable memory, such as a NAND-type flash memory, initially, an interface section with respect to the low reliable memory in a system transfers the initial program from the low reliable memory to a RAM, and thereafter, releases resetting of a CPU of the system. Next, after release of resetting, the CPU transfers a main program from the low reliable memory to the RAM in accordance with the initial program. After completion of transfer of the main program, the CPU moves the process to the main program on the RAM, and thereafter, executes the main program on the RAM (e.g., Japanese Patent Laid-Open Publication No. 2003-271391 (p. 7, FIG. 2)).
In the above-described conventional information processing device, when the initial program is transferred from the NAND-type flash memory to the RAM during the system boot, it is not possible to avoid invalid blocks in the NAND-type flash memory.
Therefore, to avoid invalid blocks, data may be read from blocks storing the initial program on a block-by-block basis during the system boot, and while reading the data, it may be determined whether or not each block is a invalid block, using a check symbol for the block. In this case, a calculated check symbol is compared with an expected value of the check symbol, and when the calculated check symbol does not match the expected value, it is determined that the block thus checked is invalid.
However, when a invalid block is detected, a start-up process needs to be stopped or the initial program needs to be transferred again from another block, resulting in a deterioration in temporal efficiency.
Check symbols, such as ECC and the like, are not effective for an error having a predetermined number of bits or more. Therefore, when invalid data of the predetermined number of bits or more is present in a check unit, there may be a possibility that the invalid data is incorrectly determined as valid data. In this case, it is likely that a invalid initial program is transferred from the NAND-type flash memory to the RAM, and is executed by the CPU.